FIG. 1 is a block diagram illustrating a configuration of a conventional semiconductor memory device.
The semiconductor memory device shown in FIG. 1 includes a memory cell CELL coupled to word lines WL0 and WL1 and a pair of bit lines BL and BLB (that is, bit line pair BL/BLB), a bit-line sense amplifier BLSA detecting data from the bit line pair BL/BLB, an input/output switch IOSW transferring data from the bit-line sense amplifier BLSA to a pair of local input/output lines LIO and LIOB (that is, local input/output pair LIO/LIOB) when an output-enable signal YI is enabled, a local input/output precharging circuit LIO PRECHARGE precharging the local input/output line pair LIO/LIOB to a precharge voltage in response to a reset signal LIORST, and a write driver WRITE DRIVER receiving data from a DQ pad (not shown) and activating the local input/output line pair LIO/LIOB in response to a write-enable signal BWEN during a writing operation.
In the semiconductor memory device of FIG. 1, the reset signal LIORST and the write-enable signal BWEN are generated in response to a column control signal YICTRL that is input as a pulse to generate the output-enable signal YI. In other words, the reset signal LIORST and the write-enable signal BWEN are generated by delaying the column control signal YICTRL (not shown) through delay paths provided thereto. As illustrated in FIG. 2, there is a period X for which the reset and write-enable signals LIORST and BWEN overlap each other in enabling term. In the period X, a current path is inadvertently formed to flow leakage current, incurring power dissipation.
Additionally, as shown in FIG. 2, there is a period t2-t3 for which data detected by the bit-line sense amplifier BLSA is interrupted to the local input/output line pair LIO/LIOB after an operation mode changes from a writing operation to a reading operation (t1) on the condition that the reset signal LIORST and the output-enable signal YI are disabled to low levels, and a precharging operation of the local input/output line pair LIO/LIOB is then completed. During this period t2-t3, as it is highly possible to induce a sensing fail due to noise while driving the bit-line sense amplifier BLSA, a sensing start time of the bit-line sense amplifier BLSA is usually delayed. However, delaying the sensing start time of the bit-line sense amplifier BLSA inevitably causes an operation rate to be lower.
Further, when the operation mode changes to the reading operation from the writing operation (t1), it is difficult to have a sufficient timing margin for precharging the local input/output line pair LIO/LIOB before the reading operation.